On the RTL Implementation of FINN Matrix Vector Unit

FPGA-based accelerators are becoming increasingly popular for deep neural network inference due to their ability scale performance with increasing degree of specialization dataflow architectures or custom data type precision. In order reduce the barrier software engineers and scientists adopt FPGAs, C++- OpenCL-based design entries high-level synthesis (HLS) have been introduced. They provide higher abstraction compared register-transfer level (RTL)-based design. HLS offers faster development time, better maintainability more flexibility in code exploration, when evaluating several options multi-dimension tensors, convolutional layers different degrees parallelism. For this reason, has adopted by DNN accelerator generation frameworks such as FINN hls4ml. paper, we present an alternative backend library FINN, leveraging RTL. We investigate evaluate, across a spectrum dimensions, pros cons RTL-based implementation versus original variant. show that smaller parameters, RTL produces significantly circuits HLS. larger circuits, however, look-up table (LUT) count is slightly higher, up around \(15\% \) . On other hand, consistently requires flip-flops (FFs) (with orders-of-magnitude difference designs) block RAMs (BRAMs) (2 × more). This also impacts critical path delay, producing \(80\% Furthermore, benefits from at-least 10 reduction time. Finally, results were validated practice using two real-world use cases, one multi-layer perceptron (MLP) used intrusion detection convolution called ResNet image recognition. Overall, since code-generate hardware design, ease entry less important. As such, gained time together some design-dependent resource benefits, make attractive alternative.